NO.025 NII Shonan Configurable Computing Workshop

Shonan Village Center

November 12 - 15, 2012 (Check-in: November 11, 2012 )


  • Peter Athanas
    • Virginia Tech, USA
  • Brad Hutchings
    • Brigham Young University, USA
  • Kentaro Sano
    • Tohoku University, Japan


Configurable computing is an emerging technology proving to be capable of providing high computational performance on a diversity of applications, including 1-D and 2-D signal processing, simulation acceleration, computer graphics, and high-performance computing. High performance is achieved by rapidly reconfiguring the functionality and interconnectivity of the computing resources to match the computational requirements of specific applications.

Rapid reconfiguration provides the illusion of having a much larger (virtual) hardware platform.

With this approach, specific application properties, such as parallelism, execution profile, and data resolution can be exploited by creating custom operators, pipelines, and interconnection pathways.

In recent years a rapidly growing interest in using reconfigurable computing architectures for realizing and developing application-specific computer systems has been observed. The advances in reconfigurable technologies, in algorithms for implementation approaches and in automatic mapping methods of algorithms into hardware and processor spaces form a new computing paradigm of computing and programming, e.g. ”Computing in Space AND in Time”. This requires different and novel approaches in engineering for developing reconfigurable systems and implementing complex algorithms, including theory, architecture structures, algorithms, design systems and industrial applications that demonstrate the benefits of this promising way of computing. The fast pace of development is not leaving industry enough time to develop the necessary theoretical foundation that underpins CAD tools, OS, designs, architectures and circuit technologies. Traditional hardware and software design processes and the tools to support them are not adequate for the design of run time reconfigurable systems.

Therefore, the plan for this seminar is to focus on the issues relevant to the development of support for run-time reconfigurable systems that can be attractive to industry. A special focus will be given to dynamically run-time reconfigurable (RTR) solutions, since system adaptation and the advantages of this technology are highly visible. Additional topics in this area of research include productivity and observability.

Programmable logic devices continue to nearly double in size with each new generation. Although computational power used to grow at this same rate, this is no longer true. As such, compilation times for programmable technologies are getting longer, not shorter. Lengthy compilation time is one of the main drawbacks to this technology and it continues to limit its applicability to many problems. It is very difficult to debug complex programs when compile times are measured in hours. Current devices continue to lack sufficient debugging capabilities.

Programmers must wait for another lengthy compile each time they need to look at a new set of signals. Because of a general lack of observability simulation continues to be the debugging tool of choice even though it is at least 1,000,000 times slower than execution on a programmable chip.

The seminar will cover: (1) architectures and techniques that support dynamic reconfiguration, productivity and debug, (2) circuit technologies, (3) system architectures, (4) physical CAD tools, (5) tools to aid in the design of RTR systems, domain-specific systems and related compilers and new (6) application domains, particularly those that can effectively exploit dynamically reconfigurable architectures. We are also interested in (7) novel approaches that enhance productivity and (8) improve observability in ways that aid in debug and verification and that hold the promise to dramatically reduce time-to-market for commercial endeavors.

In addition, now that Configurable System-on-Chip devices are beginning to appear, we are interested in attracting research that (9) develops tools and design strategies to exploit the novel aspects of these devices and that can continue to reduce overall development time.

The forum will invite experts from these various research areas to present their work and opinions. In particular, we will encourage these experts to candidly describe those key research problems that, until solved, continue to hinder advancement. The expected outcome will be the identification of key problems along with proposed technical approaches to attack these problems. Researchers who attend this meeting will be able to not help solve these problems but will also help to advertise the importance of these problems to the larger research community.

The seminar that is proposed here is an excellent opportunity to discuss the results from the mentioned projects as well as research areas with researchers from Japan, Europe, United States, Canada, Asia, and Australia.

Interdisciplinary Seminar:

Researchers and practicing engineers alike need to be able to operate in interdisciplinary environments. Not only have boundaries largely disappeared between Computer Science and Electrical Engineering, for example, but we also see that the boundaries between computing and many other fields such as computational biology, chemistry, etc., are continuing to soften. Actual surveys in the EU Project MORPHEUS describe the increased request of the industry for multidisciplinary skilled engineers. The summary of the feedback can be reported like this that software engineers needs to understand new hardware paradigms (reconfigurable computing) and hardware engineers need to understand that software defines the product at the end. Supporting this trend, new workshops like the International Workshop on Reconfigurable Computing Education (RC-Education, and the AETHER – MORPHEUS Workshop- Autumn School (AMWAS, were established in order to bring together people from different research areas. But there is more activity required to bridge these gaps. Apart from the example described above, interdisciplinary skills needs to be introduced also for physicists, chip designers and hardware architecture specialists in order to master the challenges coming up with future complex electronic systems. This seminar will bring together researchers from industry and academics with an excellent reputation and the required wide base of disciplines which targets all areas of interest for future reconfigurable architectures.