This meeting will gather researchers working on secure hardware components that support information security such as encryption and decryption, electronic signatures, and authentication. Secure hardware design is characterized by a specialized application domain (cryptography), and it is required for applications that have a reliability requirement under adversary operating conditions. Similar to other application domains such as multimedia, there is a need for fast,compact, low power and/or low energy realizations. In addition however, there is a need for secure realizations ‐ the implementations have to remain reliable and trustworthy under attacks and adversary operating conditions. This makes the application domain quite unique.

The meeting will review the state-of-the-art in secure hardware design, and it will create an open forum for the discussion of important open research questions in this fast‐evolving and important field of research. The emphasis of the meeting will be on design methods, and the systematic steps that designers use to construct secure hardware. Several of the questions that we would like to address include the following.

1. What analysis techniques are applicable to the design descriptions of secure hardware? How can risk be quantified and how can we convey the results of this analysis to the designer?
2. When is secure hardware preferable over secure software, and how can we help a designer choose between these two options? What aspects of security can be rendered more efficiently in hardware than in software?
3. How do implementation attacks (fault analysis and side‐channel leakage) affect classic hardware design issues such as reliability, design for testability, and verification? What guidelines can be defined for the hardware designer?
4. Can we define correct-by-construction techniques for secure hardware design? What aspects of cryptographic engineering are amendable to compiler techniques?
5. How to define design libraries for secure hardware design? Is the problem similar to the classic case of Intellectual Property Reuse of hardware components? Do the security properties of individual hardware components reflect on the overall design?
6. What runtime techniques are available to evaluate a secure hardware design? How can we detect implementation attacks, and what assumptions do we have to make?
7. What techniques can be used to cost-optimize secure hardware? How do we quantify the security/cost tradeoff?