No.031 Many-cores and On-chip Interconnects

I would like to discuss our 40Gbps off-chip “wireless” link technology.

I will focus on the advantages of asynchronous interconnect in SoC and NoCs. I will first present an argument of feasibility and design efficiency showing the most recent 1.2B Transistor Switch Chip by Intel that is 90% fully asynchronous. It was designed using an automated asynchronous synthesis and place-and-route flow for logic blocks and a high-performance interconnect using full-custom clock domain crossing logic, asynchronous links and cross-bars. I will then review the advantages of asynchronous design over synchronous counterparts in terms of low latency, high-performance, and robustness to process variations, aging, and temperature.

Recent studies show that there is a significant performance gap between commercial clouds and conventional clusters equipped with equivalent processors, and that cloud computing is not mature enough to support, for instance, high performance computing. This is partly due to the lack of elastic and efficient provisioning of network resources in the cloud. We therefore argue that the following research topics are important:
1. Methods for self-adaptive and predictable provisioning of network resources,
2. Methods for high-granularity service differentiation across a set of resources,
3. Methods for self-detection of failures.
4. Methods for fault-tolerance and robust computing
5. Elastic virtualization methodologies for efficient up and down scaling.

Network on chip (NoC) has become an imperative communication fabric in the era of multi-/many- core architecture design. Nevertheless, the impact of semiconductor technology scaling, emerging technology integration, and throughput oriented core architecture have made reliable and power efficient NoC design increasingly challenging. In this talk, I will first discuss the implication of nano-scale semiconductor fabrication and silicon photonic integration on NoC design and introduce cross-layer optimizations to improve NoC dependability and run-time efficiency.
I will then address NoC design issues in throughput GPGPU processors and highlight some promising design paradigms.

Historically, significant research has been done in large-scale off-chip networks and recently, there has been significant work done on on-chip networks. Each interconnection networks have different constraints and as a result, the resulting architectures can be different while still sharing some similarities. In this talk, we will explore how we can apply interconnection networks to other domains. In particular, we will discuss how interconnection networks can be leveraged in other ways – including the design of an internal switch microarchitecture and be leveraged for use as a memory network.

State Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China.
The performance of chip multiprocessor (CMP) is determined not only by the number of the processor cores integrated on a die, but also by how efficiently they collaborate with each other. With more processor cores being integrated on a die, interconnects in CMP gradually move from traditional bus interconnects to more sophisticated networks-on-chip (NoC). With CMP continuously requiring more communication bandwidths, metallic-based electrical NoC gradually becomes the bottleneck for improving the performance of CMP due to its high power consumption, limited bandwidth and long latency. Recent studies have demonstrated that photonic NoC is a potential solution to overcome the limitations of its electrical counterpart.
Many architectures for photonic NoC have been widely studied, such as Mesh, Fat Tree and Clos. While, recent studies are gradually focused on Mesh NoC due to its symmetric architecture, good scalability, simple routing algorithm and easy implementation. A series of optical devices are required to construct the optical interconnect between two processor cores, such as lasers, modulators, multiplexers, waveguides, de-multiplexers and detectors. Such a point-to-point interconnect is the simplest communication mode. However, for network application environment, the processor core is required to communicate with other processor cores. This function is usually completed by optical router, which is located at each node of photonic NoC and connects the local processor core with other remote nodes.
In this paper, we will review the status of optical modulators and routers for photonic networks-on-chip and introduce our efforts on these topics. In the first section, we will introduce the 40 Gb/s carrier-depletion Mach-Zehnder silicon optical modulator with very a large optical bandwidth. In the second section, we will introduce a universal method for constructing the N-port non-blocking optical router for photonic NoC.

We are working for an approach to executing safety-critical embedded applications dependably using redundancy available in many-core systems. In this approach, each task of applications is loaded in several processor cores, and usually two cores execute the same task simultaneously using the same
inputs. The results of the task are sent to an IO-core, and compared there. If a mismatch is found, the task is executed again, but using three cores, to find the correct results and a faulty core.
If a faulty core is successfully detected, it is excluded from the system, and tasks are continuously executed on a reconfigured system. This idea for dependable task execution is simple, but its implementation is not so straightforward. For example, how can we maintain and update the state variables of tasks for the temporary TMR execution, and how can the IO-core be implemented dependably?
How about maintaining real-time properties? We have suggestions for some of them, but there are still open issues. This talk will discuss these implementation issues for dependable task execution on many-core systems.

Optical on-chip interconnects enable significantly increased bandwidth and decreased latency in MPSoC. However, the interfaces between electronic and photonic signals imply strong constraints on the layout of the 3D architecture and may impact the system scalability. The scalability also relies on the flexibility level of the network. This presentation deals with a regular layout for an ONOC used to interconnect processing elements located on different electrical layers. The flexibility issue of the ONoC is addressed by considering the use of reconfigurable blocks on the interfaces.

Today multi-core chip-microprocessors (CMPs) contain tens of interconnected cores or tiles. As the number of CMP cores increases, on-chip interconnection networks (NoCs) are necessary to for efficient inter-tile, on-chip communication.
Unfortunately, deep sub-micro CMOS is marred by increasing susceptibility to wear-out.
Prolonged operational stress gives rise to accelerated wear-out and failure due to one of several failure mechanisms. In many-core CMPs, while an individual core’s wear-out may not necessarily be catastrophic for the system, a single fault in the NoC could render the entire chip useless. Recently proposed fault-tolerant routing algorithms respond to wear-out by rerouting traffic around faulty components and topological NoC regions so as to safely deliver inter-core communication, however, these approaches are reactive to faults. This talk explores the viability of proactive techniques to maintain NoC components through data manipulation and wear-leveling.
In particular, the talk examines the failure mechanisms expected to dominate in future process technology, and how they are influenced by network traffic generated by real application workloads. The talk then explores how these failure mechanisms, together with inherent process variation, map on a router microarchitecture under typical application workloads. Finally, we develop a wear-resistant router microarchitecture whereby the wear induced by usage is lessened through a management of the per-component, bit-transitions, balancing transition sensitive failure mechanisms against level sensitive ones.

Silicon photonics Network-on-Chips (NoCs) have　emerged as an attractive　solution to alleviate the high power consumption of traditional electronic　interconnects. In this work, we propose a fully optical ring NoC that　combines static and dynamic wavelength allocation communication mechanisms.
A different wavelength-channel is statically　allocated to each destination　node for light weight communication. Contention of simultaneous　communication requests from multiple source nodes to the destination is solved by a token based arbitration for the particular wavelength-channel.
For heavy load communication, a multiwavelength-channel is available by requesting it in execution time from source node to a special node that　manages dynamic allocation of the shared multiwavelength-channel among all nodes. We combine these static and dynamic communication mechanisms in a same network that introduces selection techniques based on message
size and congestion information. We discuss performance of the proposed photonic NoC based on preliminary simulation results.

Key words: Network-on-Chip, High-bandwidth and low power network, Silicon photonics, Wavelength allocation.