No.134 Advances in Heterogeneous Computing from Hardware to Software

• Dr. Aaron Smith, Microsoft Research, USA
• Dr. Christian Fensch, ARM Trondheim, Norway
• Dr. Hiroshi Sasaki, Columbia University, USA

• Dr. Shinpei Kato, University of Tokyo/Click IV, Japan
• Prof. Satoshi Matsuoka, Tokyo Institute of Technology/RIKEN, Japan

• Dr. Marco Aldinucci, University of Turin, Italy
• Dr. Bruno Bodin, Yale-NUS, Singapore
• Dr. Mauricio Breternitz, Lisbon University & INESC-ID Institute, Portugal
• Dr. Nick Brown, University of Edinburgh, UK
• Dr. Christophe Dubach, University of Edinburgh, UK
• Dr. Sebastian Hack, Saarland University, Germany
• Dr. Keiji Kimura, Waseda University, Japan
• Dr. Masaaki Kondo, University of Tokyo, Japan
• Dr. Takatsugu Ono, Kyushu University, Japan
• Dr. Antoniu Pop, University of Manchester, UK
• Dr. Louis-Noel Pouchet, Colorado State University, USA
• Dr. Fabrice Rastello, INRIA, France
• Prof. Sven-Bodo Scholz, Heriot-Watt University, UK
• Dr. Magnus Själander, NTNU, Norway
• Dr. Michel Steuwer, University of Glasgow, UK
• Dr. Osman Sabri Ünsal, Barcelona Supercomputing Center,  Spain
• Dr. Wim Vanderbauwhede, University of Glasgow, UK
• Dr. Yasutaka Wada, Meisei University, Japan
• Dr. Hiroshi Yamada, Tokyo University of Agriculture and Technology, Japan
• Dr. Ayal Zaks, Technion, Israel

Sunday (9/2)

• 15:00 ​-​ 19:00: Hotel Check-In
• 19:00 ​-​ 21:00: Welcome Banquet

Monday (9/3) – Room 208

• 7:30 ​-​ 9:00: Breakfast (Cafeteria “Oak”)
• 9:00 ​-​ 9:15: Short Video about NII
• 9:15 ​-​ ​10:00:​ ​Opening and Introductions
• 10:00 ​-​ ​10:30:​ ​Coffee and Discussion
• 10:30 ​-​ ​12:15:​ ​Session 1
  • # 1 AnyDSL: A Partial Evaluation Framework for Programming High-Performance Libraries, Sebastian Hack
  • # 2 Optimizing for Heterogeneous Locality, or Homogeneous Parallelism?, Ayal Zaks
  • # 3 Customized Polyhedral Compilation for Low-Power High-Level SoC Synthesis, Louis-Noel Pouchet
• 12:15 ​-​ 13:30:​ ​Lunch​ (Cafeteria “Oak”)
• 13:30 ​-​ 14:00: Group Photo
• 14:00 ​-​ 15:30: Keynote
  • A Domain-Specific Architecture for Autonomous Driving Technology, Shinpei Kato, University of Tokyo
• 15:30 ​-​ 16:00: Coffee and Discussion
• 16:00​ ​-​ ​18:00:​ ​Session 2
  • # 4 Reinforcement Learning-Based Adaptive Power Management for Energy Harvesting IoT Devices, Masaaki Kondo
  • # 5 Generating Performance Portable Code with Lift, Michel Steuwer & Christophe Dubach
  • # 6 Generating Performance Portable Code with Lift, Michel Steuwer & Christophe Dubach
  • # 7 OSCAR Compiler and OSCAR API for Heterogeneous Computing, Keiji Kimura
• 18:00 ​-​ 19:30: Dinner (Cafeteria “Oak”)

Tuesday (9/4) – Room 208

• 7:30 ​-​ 9:00: Breakfast (Cafeteria “Oak”)
• 9:00​ ​-​ ​11:00:​ ​Keynote
  • From TSUBAME3 to Post-K: Massive Scaling not only in HPC but also in Big
    Data and AI/ML, Satoshi Matsuoka, RIKEN/Tokyo Institute of Technology
• 11:00 ​-​ 11:30: Coffee and Discussion
• 11:30 ​-​ 12:00:​ ​Session 3
  • # 8 Hardware-Software Codesign for Efficient Computing, Magnus Sjalander
• 12:00​ ​-​ ​13:30:​ ​Lunch​ (Cafeteria “Oak”)
• 13:30​ ​-​ 15:30:​ Session 4
  • # 9 A Network Simulator for On/Off Links of Large-Scale Interconnection Networks, Takatsugu Ono
  • # 10 ePython: An Implementation of Python for Novel Heterogeneous Architectures, Nick Brown
  • # 11 On Finding a Sweet Spot Between Productivity and Performance and Portability —
    Experiences from the SaC Compiler Project, Sven-Bodo Scholz
• 15:30 ​-​ 16:00: Coffee and Discussion
• 16:00​ ​-​ ​18:00:​ ​Session 5
  • # 12 Reducing Memory Requirements of Scientific Computations through Multi-Stage Execution, Wim Vanderbauwhede
  • # 13 Navigating the Real-Time 3D Scene Understanding Landscape, Bruno Bodin
  • # 14 Parallelizing Compilation and Task Scheduling for Heterogeneous Platforms, Yasutaka Wada
• 18:00 ​-​ 19:30: Dinner (Cafeteria “Oak”)

Wednesday (9/5) – Room 208

• 7:30 ​-​ 9:00: Breakfast (Cafeteria “Oak”)
• 9:00​ ​-​ ​10:30:​ ​Session 6
  • # 15 Undervolting Off-the-Shelf FPGAs for Energy-Efficiency, Osman Unsal
  • # 16 NUMA Optimizations for Algorithmic Skeletons, Christian Fensch
  • # 17 e2eML: High Performance, Power Efficient Application of End to End DNN for Heterogeneous Architectures, Mauricio Breternitz
• 10:30 ​-​ 11:00: Coffee and Discussion
• 11:00​ ​-​ 12:00:​ ​Session 7
  • # 18 An OS-Level Approach for Attaining Dependability of In-Memory
    Databases, Hiroshi Yamada
  • # 19 Polyhedral Based Intermediate Representation for Inter-Procedural Code Regions, Fabrice Rastello
• 12:00​ ​-​ ​13:30:​ ​Lunch​ (Cafeteria “Oak”)
• 13:30​ ​-​ 18:15:​ ​Excursion to Great Buddha and Hase Temple
• 18:15 ​-​ 20:30: Banquet

Thursday (9/6) – Room 208

• 7:30 ​-​ 9:00: Breakfast (Cafeteria “Oak”)
• 9:30​ ​-​ ​11:30:​ ​Session 8
  • # 20 Is it Time for RISC and CISC to Die?, Aaron Smith
  • # 21 Toward Near Data Processing Service Computing, Marco Aldinucci
  • # 22 There and Back Again – Will the Human Ever Get Out of the Optimization Loop, Antoniu Pop
• 11:30 ​-​ 12:00: Closing
• 12:00​ ​-​ ​13:30:​ ​Lunch​ (Cafeteria “Oak”)

This​ ​Shonan​ ​seminar​ ​​brings​ ​together​ ​a​ ​mix​ ​of​ ​practitioners​ ​and​ ​researchers​ ​from​ ​industry​ ​and academia​ ​to​ ​discuss​ ​the​ ​latest​ ​advances​ ​and​ ​challenges​ ​in​ ​heterogeneous​ ​computing.​ ​With​ ​increasingly diminishing​ ​returns​ ​in​ ​power​ ​and​ ​performance​ ​due​ ​to​ ​the​ ​slowing​ ​of​ ​Dennard​ ​scaling​ ​and​ ​Moore’s​ ​law, the​ ​heterogeneous​ ​computing​ ​community​ ​is​ ​faced​ ​with​ ​a​ ​demanding​ ​set​ ​of​ ​challenges:

• provide​ ​increasing​ ​compute​ ​performance,
• while​ ​improving​ ​energy​ ​efficiency,
• without​ ​burdening​ ​programmers​ ​with​ ​additional​ ​complexity.

Solutions​ ​to​ ​these​ ​problems​ ​increasingly​ ​rely​ ​on​ ​interdisciplinary​ ​research​ ​and​ ​hardware/software co-design​ ​to​ ​specialize​ ​the​ ​hardware​ ​and​ ​software​ ​stack​ ​for​ ​a​ ​particular​ ​problem​ ​or​ ​application​ ​domain. Examples​ ​of​ ​recent​ ​projects​ ​are​ ​Microsoft’s​ ​Catapult​ ​datacenter​ ​accelerator​ ​which​ ​is​ ​used​ ​in​ ​production to​ ​accelerate​ ​Bing​ ​ranking​ ​and​ ​Azure​ ​networking​ ​on​ ​a​ ​cloud​ ​of​ ​reprogrammable​ ​FPGAs,​ ​Google’s Tensor​ ​Processing​ ​Unit​ ​(TPU)​ ​–​ ​a​ ​custom​ ​application-specific​ ​integrated​ ​circuit​ ​(ASIC)​ ​developed​ ​to accelerate​ ​machine​ ​learning,​ ​and​ ​Amazon’s​ ​Annapurna​ ​ASIC​ ​used​ ​to​ ​accelerate​ ​network​ ​management in​ ​Amazon​ ​datacenters.

Over​ ​the​ ​course​ ​of​ ​this​ ​seminar,​ ​attendees​ ​​participate​ ​in​ ​discussions​ ​on​ ​the​ ​latest​ ​topics​ ​and​ ​trends in​ ​heterogeneous​ ​computing.​ ​We​ ​​hold​ ​sessions​ ​covering​ ​hardware​ ​and​ ​computer​ ​architecture, development​ ​tools,​ ​operating​ ​systems​ ​and​ ​runtimes,​ ​programming​ ​models,​ ​and​ ​application​ ​workloads. These​ ​sessions​ ​include​ ​a​ ​mix​ ​of​ ​talks​ ​and​ ​open​ ​discussions​ ​led​ ​by​ ​experts​ ​in​ ​their​ ​related​ ​areas. There​ ​is​ ​ample​ ​opportunity​ ​for​ ​one​ ​on​ ​one​ ​interaction​ ​in​ ​this​ ​intimate​ ​format​ ​which​ ​we​ ​expect​ ​will allow​ ​attendees​ ​to​ ​develop​ ​new​ ​connections​ ​and​ ​research​ ​directions​ ​for​ ​future​ ​collaborations.