No.031 Many-cores and On-chip Interconnects

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NII Shonan Meeting Seminar 031

Evolutionary and Revolutionary Technologies for Low Power On-Chip Communication (Bertozzi)

The advent of networks-on-chip is far from stabilizing the domain of on-chip communication architectures for multi- and many-core systems. For the high-performance computing domain, NoCs are a non-negligible source of power dissipation. For the embedded computing domain, the NoC design point stems from a trade-off between maximum resource utilization and communication performance, ultimately ending up in a system-level energy optimization issue.
Low-power on-chip communication can be achieved via evolutionary design techniques (e.g., by removing the clock and implementing clockless switching), or by means of disruptive technologies such as on-chip optical links. This talk will address the latest research findings on these technologies, taking the viewpoint of their crossbenchmarking against (aggressive) reference NoC implementations. The ultimate source of debate will be where, when and how such technologies will become viable for actual design in industry, and about how to accelerate this process.

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