Sep 2, 2012
Challenges for Dependable Many-Core Processors (Kise)
I will discuss the dependability issues, in particular soft errors and timing errors, for many-core processors.
One of our proposals is a NoC-based DMR mechanism named SmartCore to detect transient errors on a many-core processor.
It is unique because the packet level comparison for error detection is done by the new designed NoC router.