No.031 Many-cores and On-chip Interconnects

Network on chip (NoC) has become an imperative communication fabric in the era of multi-/many- core architecture design. Nevertheless, the impact of semiconductor technology scaling, emerging technology integration, and throughput oriented core architecture have made reliable and power efficient NoC design increasingly challenging. In this talk, I will first discuss the implication of nano-scale semiconductor fabrication and silicon photonic integration on NoC design and introduce cross-layer optimizations to improve NoC dependability and run-time efficiency.
I will then address NoC design issues in throughput GPGPU processors and highlight some promising design paradigms.