Many-cores and On-chip Interconnects

NII Shonan Meeting:

@ Shonan Village Center, September 23-25, 2013

NII Shonan Meeting Report (ISSN 2186-7437):No.2013-8

Organizers

  • Tomohiro Yoneda, National Institute of Informatics, Japan
  • José Flich Cardo, Escuela Técnica Superior de Informática Aplicada, Spain
  • Jiang Xu, The Hong Kong University of Science and Technology, Hong Kong
  • Michihiro Koibuchi, National Institute of Informatics, Japan

Overview

Over the past few decades, a considerable number of studies have been conducted on the
improvement and implementation of VLSIs. It has been recognized that the performance
improvement of a single processor core is limited due to clock skew, power consumption, heat
dissipation, leakage current, instruction level parallelism, and complexity. As a result, the rise of chip
multiprocessor (CMP) and multi-processor system-on-a-chip (MPSoC) has rapidly been gaining pace,
and they have become accepted as an integral part of the modern processing architecture. In these
multiple core architectures, it has been recognized that a simple bus architecture does not scale with
the system size as the bandwidth is shared by all the cores attached to it. Thus, the concern with
on-chip networks has been growing as a feasible solution to many-core systems. Recently, it is also
reported that fully asynchronous on-chip networks for NoCs have many advantages over the
corresponding synchronous designs. On the other hand, as semiconductor process technology scales
and on-chip networks become large, routers and links that compose on-chip networks should have
tolerance against several kinds of faults. For example, even if one link or router goes down, the
remaining part of the network should continue to work. Routers and links should adapt to
performance degradation caused by effects like PMOS transistor negative bias temperature instability
(NBTI), hot carrier degradation (HCI), VDD drop, temperature increase, and so on. Also, transient
faults caused by soft-errors or noises should be tolerated. Furthermore, as more and more
complicated applications are run on NoCs, the demand for on-chip networks with
low-latency/high-throughput is increasing.

In this meeting, we would like to discuss the future direction of many-core and its on-chip
interconnect technologies related to the above issuess for supporting strong and weak scaling of
parallel applications. Our technical interests include on-chip communication technologies,
architectures, methods and applications, and asynchronous design for achieving low-power, high
reliability, low-latency and high-throughput computing toward high-performance systems that
include not only for High Performance Computing (HPC) but also embeded systems.