No.112 Theory and Practice of Data Plane Programming

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NII Shonan Meeting Seminar 112

Organizers

Nate FosterNate Foster is an Associate Professor at Cornell University and a Principal Research Engineer at Barefoot Networks. His current research focuses on the design and implementation of high-level network programming languages.

Motoyoshi Sekiya is a Senior Director of Network Systems Laboratory in Fujitsu Laboratories Ltd. His current research focus on network architecture and control system for software programmed optical / packet network. From 2010-2015 he led optical networking and transmission research at Fujitsu Labs America.

Participants

Prof. Nate Foster Cornell University USA
Mr. Motoyoshi Sekiya Fujitsu Laboratories Japan
Prof. Aditya Akella UW-Madison USA
Prof. Shingo Ata Osaka City University Japan
Dr. Sujata Banerjee HPE Labs USA
Dr. Nikolaj Bjorner Microsoft Research USA
Prof. Marco Canini KAUST Saudi Arabia
Dr. Pavol Cerny University of Colorado Boulder USA
Dr. Ping Du Univ. of Tokyo Japan
Dr. Andy Fingerhut Cisco USA
Dr. Alex Horn Fujitsu Labs of America USA
Dr. Kiyo Ishii AIST Japan
Dr. Changhoon Kim Barefoot Networks USA
Dr. Yoshiaki Kiriha Univ. of Tokyo Japan
Prof. Akihiro Nakao The University of Tokyo Japan
Dr. Srinivas Narayana MIT USA
Dr. Naoki Oguchi Fujitsu Laboratories LTD. Japan
Prof. Ruzica Piskac Yale University USA
Prof. Vyas Sekar Carnegie Mellon University USA
Prof. Norihiko Shinomiya Soka Univ Japan
Prof. Kohei Shiomoto Tokyo City University Japan
Mr. Steffen Smolka Cornell University USA
Prof. Robert Soule University of Lugano Switzerland
Prof. Laurent Vanbever ETH Zurich Switzerland
Dr. Xi Wang Fujitsu Labs of America USA
Dr. Nicholas Zhang Huawei China

Schedule

Sunday, February 25, 2018

15:00 – : Check-in
19:00 – 21:00: Welcome Banquet

Monday, February 26, 2018

07:30 – 09:00: Breakfast
09:00 – 09:15: Welcome (Nate Foster & Motoyoshi Sekiya)
09:15 – 09:45: Introductions
09:45 – 10:30: Changhoon Kim
10:30 – 11:00: Break
11:00 – 11:45: Vyas Sekar “Programming Stateful Dataplanes”
11:45 – 12:00: Discussion
12:00 – 13:30: Lunch
13:30 – 14:00: Group photo shoot
14:00 – 14:45: Laurent Vanbever
14:45 – 15:40: Working Group Discussion
15:40 – 16:00: Break
16:00 – 16:30: Working Group Readouts
16:30 – 16:45: Ruzica Piscak “Verification and Repair of Firewalls”
16:45 – 17:00: Norihiko Shinomiya “Cycle-Based Traffic Balancing Method for Clustered Network with Multiple SDN Controllers”
18:00 – 19:30: Dinner

Tuesday, February 27, 2018

07:30 – 09:00: Breakfast
09:00 – 09:45: Srinivas Narayan
09:45 – 10:30: Alex Horn
10:30 – 11:00: Break
11:00 – 12:00: Session
12:00 – 13:30: Lunch
13:30 – 14:15: Akihiro Nakao
14:15 – 15:30: Session
15:40 – 16:00: Break
16:00 – 17:00: Session
18:00 – 19:30: Dinner

Wednesday, February 28, 2018

07:30 – 09:00: Breakfast
9:00– 10:30: Session
10:30– 11:00: Break
11:00– 12:00: Session
12:00 – 13:30: Lunch
13:30 – 20:45: Excursion and Dinner at “Minemoto”

Thursday, March 1, 2018

07:30 – 09:00: Checkout & breakfast
09:00 – 10:30: Session
10:30 – 10:45: Break
10:45 – 12:00: Session
12:00 – 13:30: Lunch

Overview

Networks have traditionally been built out of fixed-function devices such as routers, switches, and firewalls that provide good performance, but are difficult to customize or extend with new functionality. Recently a number of researchers have started to develop new kinds of devices in which nearly every feature, from the packet parser, to the data processing pipeline, to the traffic manager, is programmable. They have also developed accompanying languages, compilers, and verification tools for programming and reasoning about these devices. These advances have made it possible to customize the structure and functionality of a network to suit specific applications. Already, programmers have started to develop novel applications such in-network telemetry, which provides fine-grained visibility into network state, as well as data plane implementations of distributed protocols, which can improve performance by orders of magnitude compared to end host implementations.

However, despite tremendous progress, a number of important research questions remain:

  • Architecture: What features do programmable data planes require at the hardware level? Are there certain designs that are inevitable and others that fundamentally do not make sense? What primitives, techniques, and optimizations are needed to achieve good performance? What are the fundamental tradeoffs in designs based on traditional switch ASICs, FPGAs, NPUs, programmable NICs, and software switches?
  • Programming Languages: What features should high-level languages for programmable data planes provide? Are there essential constructs or those that should be left out? What is the role of types, both for catching bugs and enabling compiler analyses and optimizations? What are the right concurrency models for programmable data planes, both on a single device and across multiple devices?
  • Compilers: What are the key optimizations in the domain of data plane programming? Can classic ideas from the compiler community such as speculation, prediction, and stochastic super-optimization be adapted to the networking domain further accelerate data plane programs?
  • Formal Verification: What data plane properties can we check automatically? It is possible to add notions of state to existing data plane verification tools ? How can we extend these frameworks to enable reasoning about quantitative and probabilistic properties?
  • Applications: What are the “killer” applications for programmable data planes? Some early adopters have identified some promising ideas, but it is clear that these have only scratched the surface.

The technical agenda will be organized around four distinct kinds of activities. First, to help establish a common background and vocabulary, we plan to start the workshop with longer invited tutorials in each of the categories above from experts. Second, we plan to have shorter presentations of research highlights to give a sense of current research trends and, as a secondary goal, to help promote the careers of junior researchers. Third, we plan to organize interactive working groups, technical panels, and debates, to help encourage cross-fertilization and make progress on more open-ended questions. Fourth, we plan to invite participants to present hands-on demos. We plan to write a survey article after the workshop and submit it for publication in a venue such as ACM SIGCOMM CCR.