No.031 Many-cores and On-chip Interconnects

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NII Shonan Meeting Seminar 031

Why Asynchronous Interconnect? (Beerel)

I will focus on the advantages of asynchronous interconnect in SoC and NoCs. I will first present an argument of feasibility and design efficiency showing the most recent 1.2B Transistor Switch Chip by Intel that is 90% fully asynchronous. It was designed using an automated asynchronous synthesis and place-and-route flow for logic blocks and a high-performance interconnect using full-custom clock domain crossing logic, asynchronous links and cross-bars. I will then review the advantages of asynchronous design over synchronous counterparts in terms of low latency, high-performance, and robustness to process variations, aging, and temperature.

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