No.031 Many-cores and On-chip Interconnects

This talk presents how to layout many-core processors SoCs. Currently, the layout design time is quite significant for large scale LSIs, because of the complexity involved with the verification of timing and signal integrity constraints. The size and complexity of many-core SoC, limit the possibility to perform hierarchical layout designs. However, there are various methods for the hierarchical layout designs. In general, a strict hierarchical design method can provide ease of reconfigurability, but it results in worse area and timing with respect to a flat layout method, which, on the other hand, does not provide reconfigurability. To solve these problems and questions about the hierarchical layout design, the trials and the evaluations are applied for Network On Chip (NoC), which is the typical implementation of many-core processors SoC. A NoC which connects IP cores by network interfaces can be easily reconfigured during place and route and it has a strong regularity. In this talk, the several layout evaluation results of NoC and the discussions are presented. For example, it is confirmed that the strict hierarchical design method even makes the poor layout results for NoC. Furthermore, a reconfigurable layout method for Networks-on-Chip (NoCs) based on partial re-layout is introduced. I also welcome discussions on layout issues for many-core processor SoC.