No.031 Many-cores and On-chip Interconnects

A network-on-chip (NOC) enables the integration of the hundreds and even thousands of cores in a many core system-on-chip (SOC). Efficient testing and design-for-testability techniques must be developed for such “monster” chips. I will describe test-data delivery optimization algorithms for manycore SOCs with hundreds of cores, where a network-on-chip (NOC) is used as the interconnection fabric. I will first present an optimization algorithm based on a subset-sum formulation to solve the test-delivery problem in NOCs with arbitrary topology that use dedicated routing. Next I will propose an algorithm for the important class of NOCs with grid topology and XY routing. The proposed algorithm is the first to co-optimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization of such NOCs. Test-time minimization is modeled as an NOC partitioning problem and solved with dynamic programming in polynomial time. Both the proposed methods yield high-quality results and are scalable to large SOCs with many cores. Test scheduling under power constraints is also incorporated in the optimization framework.