No.031 Many-cores and On-chip Interconnects

State Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China.
The performance of chip multiprocessor (CMP) is determined not only by the number of the processor cores integrated on a die, but also by how efficiently they collaborate with each other. With more processor cores being integrated on a die, interconnects in CMP gradually move from traditional bus interconnects to more sophisticated networks-on-chip (NoC). With CMP continuously requiring more communication bandwidths, metallic-based electrical NoC gradually becomes the bottleneck for improving the performance of CMP due to its high power consumption, limited bandwidth and long latency. Recent studies have demonstrated that photonic NoC is a potential solution to overcome the limitations of its electrical counterpart.
Many architectures for photonic NoC have been widely studied, such as Mesh, Fat Tree and Clos. While, recent studies are gradually focused on Mesh NoC due to its symmetric architecture, good scalability, simple routing algorithm and easy implementation. A series of optical devices are required to construct the optical interconnect between two processor cores, such as lasers, modulators, multiplexers, waveguides, de-multiplexers and detectors. Such a point-to-point interconnect is the simplest communication mode. However, for network application environment, the processor core is required to communicate with other processor cores. This function is usually completed by optical router, which is located at each node of photonic NoC and connects the local processor core with other remote nodes.
In this paper, we will review the status of optical modulators and routers for photonic networks-on-chip and introduce our efforts on these topics. In the first section, we will introduce the 40 Gb/s carrier-depletion Mach-Zehnder silicon optical modulator with very a large optical bandwidth. In the second section, we will introduce a universal method for constructing the N-port non-blocking optical router for photonic NoC.