No.031 Many-cores and On-chip Interconnects

Many-cores come in many flavors: mesh-noc tiled arrays (e.g.
Tilera), hierarchical multi-cores (e.g. Rigel), hierarchical multi-threading
(e.g. Nvidia), SIMD and associative processors. Comparing them for
performance, power, area and ease of programming is a fuzzy art at best,
typically requiring the construction of complete applications, optimizing
them separately for each architecture and executing or simulating them. The
results are not always convincing and we often end up just where we started.
We attempt to extend mathematical analysis of architecture to this field. A
model accounts for performance and power of cores as a function of area and
other parameters. On-chip memories are also modeled. Basic axioms such as
Amdahl’s law and Pollack’s rule are employed to formulate the model.
However, adapting the model to a variety of many-core architectures remains
a challenge.