No.031 Many-cores and On-chip Interconnects

Optical on-chip interconnects enable significantly increased bandwidth and decreased latency in MPSoC. However, the interfaces between electronic and photonic signals imply strong constraints on the layout of the 3D architecture and may impact the system scalability. The scalability also relies on the flexibility level of the network. This presentation deals with a regular layout for an ONOC used to interconnect processing elements located on different electrical layers. The flexibility issue of the ONoC is addressed by considering the use of reconfigurable blocks on the interfaces.