No.031 Many-cores and On-chip Interconnects

Today multi-core chip-microprocessors (CMPs) contain tens of interconnected cores or tiles. As the number of CMP cores increases, on-chip interconnection networks (NoCs) are necessary to for efficient inter-tile, on-chip communication.
Unfortunately, deep sub-micro CMOS is marred by increasing susceptibility to wear-out.
Prolonged operational stress gives rise to accelerated wear-out and failure due to one of several failure mechanisms. In many-core CMPs, while an individual core’s wear-out may not necessarily be catastrophic for the system, a single fault in the NoC could render the entire chip useless. Recently proposed fault-tolerant routing algorithms respond to wear-out by rerouting traffic around faulty components and topological NoC regions so as to safely deliver inter-core communication, however, these approaches are reactive to faults. This talk explores the viability of proactive techniques to maintain NoC components through data manipulation and wear-leveling.
In particular, the talk examines the failure mechanisms expected to dominate in future process technology, and how they are influenced by network traffic generated by real application workloads. The talk then explores how these failure mechanisms, together with inherent process variation, map on a router microarchitecture under typical application workloads. Finally, we develop a wear-resistant router microarchitecture whereby the wear induced by usage is lessened through a management of the per-component, bit-transitions, balancing transition sensitive failure mechanisms against level sensitive ones.