No.031 Many-cores and On-chip Interconnects

A massively parallel application run on a future supercomputer is expected to require very low end-to-end latencies. Most of off-chip interconnection topologies does not consider cable delay (i.e. near light speed), because switch delay (some hundred nanoseconds) dominates the end-to-end latency. So, what if a ultra-low-delay (some ten nanoseconds) switch becomes available in the near future? Do traditional off-chip topologies work well in those situations? We would like to discuss about the topology design for the future supercomputing systems, as well as for the future on-chip networks.