Many-cores and On-chip Interconnects

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NII Shonan Meeting Seminar 031

Organizers & Materials

Self-introduction Slides(for participants only)

Presentation Slides (for participants only)

Memorial photo

Photo (walking)

Tomohiro Yoneda, Jose Flich, Jiang Xu, and Michihiro Koibuchi

Participants

Ajima, Yuuichirou (title/abst)

Amano, Hideharu(title/abst)

Beerel, Peter (title/abst)

Bertozzi, Davide (title/abst)

Le BEUX, Sébastien (title/abst)

Chakrabarty, Krishnendu (title/abst)

Flich, Jose (title/abst)

Fujiwara, Ikki(title/abst)

Ginosar, Ran (title/abst)

Gratz, Paul (title/abst)

Kim, John (title/abst)

Kise, Kenji (title/abst)

Koibuchi, Michihiro (title/abst)

Li, Tao (title/abst)

Liang, Yun (title/abst)

Lysne, Olav (title/abst)

Matsutani, Hiroki(title/abst)

Nakamura, Yuichi (title/abst)

Xu, Jiang (title/abst)

Yang, Lin (title/abst)

Yoneda, Tomohiro (title/abst)

Yoshinaga, Tsutomu (title/abst)

Preliminary Program

Introduction: Please introduce yourself on Monday morning with 1-2 slides (within 2 minutes), answering the following questions:
? Effort of your activity: research, education, governance/management, social service, and others. e.g. 40% for research, 20% for education, 25% for management, 15% for social service.
? What is the incentive to your research activity?
? Which journals/conferences do you well survey?

Talks: up to 20 minutes plus 20 minutes of discussion

For more details;
PLAN A (If the weather is fine on Monday).
PLAN B (If the weather is rainy on Monday).

Overview

Over the past few decades, a considerable number of studies have been conducted on the improvement and implementation of VLSIs. It has been recognized that the performance improvement of a single processor core is limited due to clock skew, power consumption, heat dissipation, leakage current, instruction level parallelism, and complexity. As a result, the rise of chip multiprocessor (CMP) and multi-processor system-on-a-chip (MPSoC) has rapidly been gaining pace, and they have become accepted as an integral part of the modern processing architecture. In these multiple core architectures, it has been recognized that a simple bus architecture does not scale with the system size as the bandwidth is shared by all the cores attached to it. Thus, the concern with on-chip networks has been growing as a feasible solution to many-core systems. Recently, it is also reported that fully asynchronous on-chip networks for NoCs have many advantages over the corresponding synchronous designs. On the other hand, as semiconductor process technology scales and on-chip networks become large, routers and links that compose on-chip networks should have tolerance against several kinds of faults. For example, even if one link or router goes down, the remaining part of the network should continue to work. Routers and links should adapt to performance degradation caused by effects like PMOS transistor negative bias temperature instability (NBTI), hot carrier degradation (HCI), VDD drop, temperature increase, and so on. Also, transient faults caused by soft-errors or noises should be tolerated. Furthermore, as more and more complicated applications are run on NoCs, the demand for on-chip networks with low-latency/high-throughput is increasing.

In this meeting, we would like to discuss the future direction of many-core and its on-chip interconnect technologies related to the above issues for supporting strong and weak scaling of parallel applications. Our technical interests include on-chip communication technologies, architectures, methods and applications, and asynchronous design for achieving low-power, high reliability, low-latency and high-throughput computing toward high-performance systems that include not only for High Performance Computing (HPC) but also embedded systems.

FYI

IEEE MCSoC-13 (The International Symposium on Embedded Multicore/Many-core System-on-Chip) is held in Tokyo (NII), 26th Sep -28th Sep, 2013.
MCSoC is independent of Shonan meeting, but some of participants will attend MCSoC, because Shonan seminar and IEEE MCSoC will be opened at the same week in Japan.

From Airports to Shonan Village Center

See Shonan Village website for the detailed access information. We assume people will arrive at Tokyo Narita airport or Tokyo Haneda airport. In both cases, we recommend taking a train to Zushi area (roughly 2 hours) firstly, then taking a taxi or a bus to Shonan Village Center (20-30 minutes).

From Tokyo Narita Airport to Zushi area
First, take JR Narita Express and change at “Yokohama” station to JR Yokosuka Line, and get off at JR Zushi station.

From Tokyo Haneda Airport to Zushi area
First, take Keikyu Haneda Airport Line and change at Keikyu Kamata station to Keikyu Line. At Kanazawa-Hakkei station, change to Keikyu Zushi Line, and finally get off at Shin-Zushi station.

From JR Zushi or Keikyu Shin-Zushi station to Shonan Village Center
– Bus option : 30 minutes ride, 340 yen. Here is the bus time table from JR Zushi to Shonan Village Center. (Keikyu Shin-Zushi is basically the same timetable, but 2 minutes plus).
– Taxi option : 20 minutes ride, 2,500 to 3,000 yen. Here is a PDF file for your help, when showing destinations to a taxi driver.

To check train schedule in Japan
Hyperdia Hitachi Systems:
e.g.
1) From NARITA AIRPORT TERMINAL 1 to Zushi
2) From NARITA AIRPORT TERMINAL 2 to Zushi
3) From HANEDA AIRPORT INTERNATIONAL BUILDING to Zushi
4) From HANEDA AIRPORT INTERNATIONAL BUILDING to SHINZUSHI

(The travel info. above and the picture below is basically from http://shonan.nii.ac.jp/seminar/036/)
access_map04_big

Plan A (If the weather is fine on Monday)

Monday (Sep. 23)
Chip Design and Networks

○ 8:45 ?10:45
Welcome, Introducing ourselves(Chair: Tomohiro Yoneda)

Many-core Design
 Hideharu Amano
 Ran Ginosar

○ 11:00 ?12:20
Off-chip Network Design and Layout (Chair: John Kim)
 Michihiro Koibuchi
 Yuichi Nakamura

○ 1:30 ?3:30
Walking

○ 3:40 ? 5:00
On- and Off-chip Network Design (Chair: Hideharu Amano)
Ikki Fujiwara
  John Kim

○ 5:10-6:30
Off-chip Networks (Chair: Jose Flich)
 Yuuichirou Ajima
 Olav Lysne

—————

Tuesday (Sep. 24)
NoC

○ 8:45 ?10:45
NoC Design (Chair: Tao Li)
 Hiroki Matsutani
 Davide Bertozzi
Krishnendu Chakrabarty

○ 11:00 ?12:20
Photonic Interconnect (1) (Chair: Davide Bertozzi)
 Sébastien Le Beux
 Lin Yang

○ 1:30 ?2:50
Photonic Interconnect (2) (Chair: Sébastien Le Beux)
 Jiang Xu
 Tsutomu Yoshinaga

○ 3:00 ? 5:00
Async Design & NoC (Chair: Ran Ginosar)
 Peter Beerel
 Tomohiro Yoneda
 Paul V. Gratz

○ 5:15-6:30
Panel: Interconnects for Manycores
Moderator: Jiang Xu, Hong Kong University of Science and Technology
Panelist: Yuuichirou Ajima, Fujitsu
Ran Ginosar, Technion
Jose Flich Cardo, Universidad Politecnica de Valencia
Davide Bertozzi, University of Ferrara
Paul Gratz, Texas A&M University
Michihiro Koibuchi, National Institute of Informatics

—————

Wednesday (Sep. 25)
Many-core Architecture

○ 8:45 ?10:05
Many-core Architecture (Chair: Olav Lysne)
 Tao Li
 Eric Liang

○ 10:15-11:35
Many-core Architecture and NoC (Chair: Eric Liang)
 Kenji Kise
Jose Flich
 
○ 11:45-12:00
Wrap-up (Chair: Jose Flich)

○ 1:45
Departure

Plan B (If the weather is rainy on Monday)

Monday (Sep. 23)
Chip Design and Networks

○ 8:45 ?10:45
Welcome, Introducing ourselves (Chair: Tomohiro Yoneda)
Many-core Design
 Hideharu Amano
 Ran Ginosar

○ 11:00 ?12:20
Off-chip Network Design and Layout (Chair: John Kim)
 Michihiro Koibuchi
 Yuichi Nakamura

○ 2:00 ?3:20
On- and Off-chip Network Design (Chair: Hideharu Amano)
Ikki Fujiwara 
John Kim

○ 3:40 ? 5:00
Off-chip Networks (Chair: Jose Flich)
 Yuuichirou Ajima
 Olav Lysne

○ 5:15-6:15
Panel: Interconnects for Manycores
Moderator: Jiang Xu, Hong Kong University of Science and Technology
Panelis: Yuuichirou Ajima, Fujitsu
Ran Ginosar, Technion
Jose Flich Cardo, Universidad Politecnicade Valencia
Davide Bertozzi, University of Ferrara
Paul Gratz, Texas A&M University
Michihiro Koibuchi, National Institute of Informatics
—————

Tuesday (Sep. 24)
NoC

○ 8:45 ?10:45
NoC Design (Chair: Tao Li)
 Hiroki Matsutani
 Davide Bertozzi
Krishnendu Chakrabarty

○ 11:00 ?12:20
Photonic Interconnect (1) (Chair: Davide Bertozzi)
 Sébastien Le Beux
 Lin Yang

○ 2:00 ?3:20
Photonic Interconnect (2) (Chair: Sébastien Le Beux)
 Jiang Xu
 Tsutomu Yoshinaga

○ 3:40 ? 5:40
Async Design & NoC (Chair: Ran Ginosar)
 Peter Beerel
 Tomohiro Yoneda
 Paul V. Gratz

—————

Wednesday (Sep. 25)
Many-core Architecture

○ 8:45 ?10:05
Many-core Architecture (Chair: Olav Lysne)
 Tao Li
 Eric Liang

○ 10:15-11:35
Many-core Architecture and NoC (Chair: Eric Liang)
 Kenji Kise
Jose Flich

○ 11:45-12:00
Wrap-up (Chair: Jose Flich)

○ 1:45
Departure

Building Block Networks with Wireless Inductive Coupling Though-Chip Interface (Amano)

Inductive Coupling Though-Chip Interface (TCI) connects stacked chips by
coils only with existing IC interconnections. Over-Gb/s data transfer
rate can be achieved with less than 10mW power dissipation. Parallel data bits
can be multiplexed into one single coil and burst-transferred.
With TCI, a high speed network can be formed just by stacking multiple chips
in various forms. A heterogeneous multi-core system called Cube-1 consisting of
an embedded CPU and multiple accelerators is now available.
By using TCI, a building block network, which
has intermediate properties between Network-on-Chips and wireless ad-hoc
networks, is formed by combining chips in various structures.

Does light speed affect topologies? (Fujiwara)

A massively parallel application run on a future supercomputer is expected to require very low end-to-end latencies. Most of off-chip interconnection topologies does not consider cable delay (i.e. near light speed), because switch delay (some hundred nanoseconds) dominates the end-to-end latency. So, what if a ultra-low-delay (some ten nanoseconds) switch becomes available in the near future? Do traditional off-chip topologies work well in those situations? We would like to discuss about the topology design for the future supercomputing systems, as well as for the future on-chip networks.